1. Field of the Invention
This invention relates to a solid state imaging device including a plurality of solid-state imaging-device chips and which is suitable for use in an image input apparatus or the like. This invention also relates to a method for assembling such a solid state imaging device.
2. Description of the Related Art
A conventional solid state imaging device in which a plurality of solid-state imaging-device chips are arranged in a common plane has a structure, for example, like that shown in FIG. 19A. The solid state imaging device shown in FIG. 19A is an in-line arrangement type of solid state imaging device in which a plurality of rectangular solid-state imaging-device chips 10, which are called CCD (charge coupled device) linear image sensors, are arranged in a straight line. FIG. 19B is a cross-sectional view of this solid state imaging device. As shown in FIGS. 19A and 19B, the plurality of solid-state imaging-device chips 10 are secured to a package board 20 by die bond resin (not shown). Wiring portions 23 are formed on the package board 20, and external leads 24 connected to the corresponding wiring portions 23 are fixed at an outer edge of the package board 20. A glass lid 21 is mounted on the package board 20 by adhesive resin 26, defining a space for hermetically enclosing the portion on which the solid-state imaging-device chips 10 are carried.
As shown in FIG. 19C, bonding pads 12 are formed on each of the solid-state imaging-device chips 10, and these bonding pads 12 are electrically connected by wires 13 to corresponding terminals 22 connected to the respective wiring portions 23. Picture elements 11, such as photodiodes, a light receiving portion, are disposed on the upper surface (as viewed in the figure) of the solid-state imaging-device chip 10, and this plurality of picture elements 11 is arranged in series to as a picture-element array 1.
The solid state imaging device having the above-described construction is primarily used as an image input device for scanning a document for readout of information in a facsimile, a copying machine or the like. For instance, in order to scan an A3-size document for readout of information, it has been necessary to assemble a solid state imaging device having an effective readout width of at least 290 mm. However, the maximum length of the solid-state imaging-device chip 10 such as a CCD linear image sensor, which utilizes silicon semiconductor technology or the like, is limited by the diameter of a silicon substrate which is employed in forming this image sensor. Even if a silicon substrate of, for example, a 6 inch size is employed, the obtained sensor length is actually on the order of 100 mm since the number of chips to be cut from one wafer needs to be made large to some extent. Accordingly, in order to assure the effective readout width mentioned above, the plurality of solid-state imaging-device chips 10 are arranged as shown in FIG. 19C so that the picture-element arrays 1 are arranged in a straight line.
A method for producing a solid state imaging device comprising the aforesaid plurality of solid-state imaging-device chips 10 is explained with reference to the flow chart shown in FIG. 20.
First of all, in Step S1, a plurality of solid-state imaging-device chips 10 which are formed on a silicon substrate using silicon processing techniques are electrically measured and checked in terms of characteristics, operating performance and the like (wafer test). On the basis of the result of this wafer test, non-conforming chips are discriminated from conforming chips.
Subsequently, in Step S2, this silicon substrate is divided into individual chips by dicing. Of the solid-state imaging-device chips 10 thus divided, only the required number of chips which have been accepted as conforming articles in the wafer test of Step S1, for example, five chips are extracted. Then, in Step S3, these five chips are sequentially positioned on the package board 20 shown in FIG. 19A, and adhesively fixed thereto with die bond resin. Then, in Step S4, the bonding pads of each of the chips 10 are wire-bonded to the corresponding terminals 22 on the package board 20 by the wires 13.
Subsequently, in Step S5, the glass lid 21 is adhesively fixed to the package board 20 using the adhesive resin 26 in order to protect the solid-state imaging-device chips 10.
Through the steps described above, the solid state imaging device in which the five solid-state imaging-device chips 10 are arranged along a line is assembled. In order to check whether failure has occurred in each chip 10 during the assembling steps, after all the assembling steps have been completed, the characteristics of each chip 10 are again measured and evaluated (final test) in Step S6. This final test may be conducted in Step S7 of FIG. 20 immediately before Step S5, which is a glass-lid bonding step.
The foregoing is an explanation of an in-line arrangement type of solid state imaging device in which the plurality of solid-state imaging-device chips 10 are arranged in a straight line. Another known type of solid state imaging device uses a staggered arrangement of solid state imaging devices, such as shown in FIGS. 21A to 21C. In this solid state imaging device, the plurality of solid-state imaging-device chips 10 are arranged on the package board 20 in such a manner that each of the chips 10 alternately overlaps the adjacent chip 10 to a slight extent. Accordingly, no gap in the scan direction is present even at the junctions between the adjacent chips 10, and it is therefore possible to enjoy the advantage that image data can be read without omission. However, because of the overlapped arrangement, a circuit for correcting time and space in the scan direction is needed.
The basic structure of the above-described conventional staggered arrangement type of solid state imaging device is substantially the same as that of the in-line arrangement type of solid state imaging device, and the assembling method is also basically identical to the method shown in the flow of FIG. 20.
As described previously, in the wafer test of Step S1, it is determined whether the solid-state imaging-device chips 10 to be used in the solid state imaging device of the type described are conforming articles or non-conforming articles. Accordingly, the conforming articles alone are collected and assembled into the solid state imaging device. In practice, however, defects or failure of electrical characteristics may take place in the chips due to foreign matter clinging to the chips or to damage caused thereto in a dicing step, a die-bonding step, or a wire-bonding step after the wafer test, or during handling of the chips in these steps. For this reason, the conventional solid state imaging device is again subjected to the test (final test) in either Step S6 after the glass-lid bonding step is carried out in Step S5 of FIG. 20 or in Step S7 after the wire-bonding step is carried out in Step S4. In this manner, in the prior art, the final decision is made as to whether the solid state imaging device is a conforming article or a non-conforming article.
Accordingly, in a case where it is found in the final test that a defect has occurred in one chip of a solid state imaging device having, for example, a five chip construction, if no action is taken, it follows that the solid state imaging device consisting of the combination of this plurality of solid-state imaging-device chips 10 is a non-conforming article. As a result, not only the non-conforming chip but the four conforming chips will be regarded as non-conforming chips. Accordingly, it has been impossible to avoid low production yield and to use conforming solid-state imaging-device chips 10 form a non-conforming device.
To overcome such problems, a method (chip replacement method) of replacing the non-conforming chip found in the final test with another conforming chip is proposed. However, since the chips 10 are commonly arranged extremely close to each other in order to minimize the gaps between the adjacent chips 10, it has been difficult to cut the connections made by the relevant wires 13 and remove the non-conforming chip alone from among the chips 10 arranged by overcoming the adhesive force of the die bond resin without causing damage to the other conforming chips. Even if the non-conforming chip alone could be removed, it would be difficult to remove the die bond remaining on the package board 20 without foreign matter such as dust clinging to the other conforming chips. In addition, it is extremely difficult to newly insert a conforming chip into the limited space and fix it there by die bonding without adversely affecting the other chips. Moreover, the process is extremely complicated due to various factors such as the necessity of a wire bonding step, and it is nearly impossible, rather than merely difficult, to complete the sequence of steps described above without inducing defects such as physical damage, adhesion of foreign matter or the like or failure of electrical characteristics in the other conforming chips.
These problems apply not only to the in-line arrangement type of solid state imaging device but to the staggered arrangement type of solid state imaging device.
The above chip replacement is not needed only in the case of replacement of a non-conforming chip with a conforming chip. For example, if electrical characteristics such as sensitivity, dark current value, saturation signal level and spectral sensitivity characteristics of each solid-state imaging-device chip are not within a proper range and certain variations in the electrical characteristics are found among the chips, it may also be necessary to replace a chip, that is to say, to replace a particular chip with another chip having the desired characteristics. However, it is still difficult to carry out such a chip replacement.
In order to improve, the reliability of handling and to enable chip testing before solid-state imaging-device chips separated from a wafer are fixed to a package board, the present applicant has disclosed another type of solid state imaging device in Japanese Published Patent Application No. 62-279671. This solid state imaging device is produced by preparing a plurality of sub-kits by carrying each solid-state imaging-device chip on a base which has long sides shorter than the chip and which has short sides longer than the chip and arranging the plurality of sub-kits on a package board. The arrangement of this solid state imaging device allows chip replacement after assembly, but since the length of the chip is greater than that of the base, the end faces of adjacent chips may be damaged by contact with each other during positioning of the sub-kits.